View EP2C8_43291.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www..com
Section IV. I/O Standards
This section provides information on CycloneTM II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters:

Chapter 10, Selectable I/O Standards in Cyclone II Devices Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices
Revision History
The table below shows the revision history for Chapters 10 and 11. Chapter(s)
10
Date / Version
Changes Made
November 2004, Updated Table 10-7. v1.1 June 2004, v1.0 Added document to the Cyclone II Device Handbook. Updated Table 11-1. Updated Figures 11-4, 11-5, 11-7, and 11-8.
www..com
11 November 2004, v1.1

June 2004, v1.0
Added document to the Cyclone II Device Handbook.
Altera Corporation
Section IV-1 Preliminary
www..com www..com 4U
www..com
I/O Standards
Cyclone II Device Handbook, Volume 1
www..com
Section IV-2 Preliminary
Altera Corporation
www..com www..com 4U
www..com
Chapter 10. Selectable I/O Standards in Cyclone II Devices
CII51010-1.1
Introduction
The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and LVDS compatibility allow CycloneTM II devices to connect to other devices on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera(R) Quartus(R) II software, the Cyclone II device family enables system designers to use low cost FPGAs while keeping pace with increasing design complexity. This chapter is a guide to understanding the input and output capabilities of the Cyclone II devices, including:

www..com
f
For information on hot socketing, see the Hot Socketing, ESD & Power-On Reset chapter in Volume 1 of the Cyclone II Device Handbook. Cyclone II devices support the I/O standards shown in Table 10-1.
Supported I/O standards Cyclone II I/O banks Programmable current drive strength I/O termination Pad placement and DC guidelines
Supported I/O Standards
f
See the DC Characteristics & Timing Specifications chapter in Volume 1 of the Cyclone II Device Handbook, for more details on the I/O standards discussed in this section, including target data rates and voltage values for each I/O standard.
Altera Corporation November 2004
10-1 Preliminary
www..com www..com 4U
www..com
Supported I/O Standards
f
See the External Memory Interfaces in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook for information on the I/O standards supported for external memory applications.
Table 10-1. Cyclone II Supported I/O Standards & Constraints (Part 1 of 2) VCCIO Level I/O Standard Type Input Output
3.3-V LVTTL and LVCMOS 2.5-V LVTTL and LVCMOS 1.8-V LVTTL and LVCMOS 1.5-V LVCMOS SSTL-2 class I SSTL-2 class II Single ended Single ended Single ended Single ended Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Single ended 3.3 V/ 2.5 V 3.3 V/ 2.5 V 1.8 V/ 1.5 V 1.8 V/ 1.5 V 2.5 V 2.5 V 1.8 V 1.8 V 1.8 V 1.8 V 1.5 V 1.5 V 3.3 V (4) 2.5 V (4) 1.8 V 3.3 V 2.5 V 1.8 V 1.5 V 2.5 V 2.5 V 1.8 V 1.8 V 1.8 V 1.8 V 1.5 V 1.5 V 3.3 V 2.5 V (4) 1.8 V (4)
Top & Bottom I/O Pins
Side I/O Pins User I/O Pins v v v v v v v
(1)
CLK, User I/O CLK, PLL_OUT DQS Pins DQS v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
(1)
v v v v v v v
(1)
SSTL-18 class I
www..com
v
(1)
SSTL-18 class II HSTL-18 class I HSTL-18 class II HSTL-15 class I HSTL-15 class II PCI and PCI-X (2)
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v v
(5)
v v
v
Differential SSTL-2 class I or Pseudo class II differential (3)
v
(5)
Differential SSTL-18 class I or class II
Pseudo differential (3)
v (6) v
(5)
v
(5)
10-2 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Table 10-1. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2) VCCIO Level I/O Standard Type Input Output
Differential HSTL-15 class I or class II Pseudo differential (3) (4) 1.5 V (4) 1.8 V 2.5 V (4) 3.3 V/ 2.5 V/ 1.8 V/ 1.5 V 1.5 V (4) 1.8 V (4) 2.5 V 2.5 V (4)
Top & Bottom I/O Pins
Side I/O Pins User I/O Pins
CLK, User I/O CLK, PLL_OUT DQS Pins DQS v (6) v
(5)
v
(5)
Differential HSTL-18 class I or class II
Pseudo differential (3)
v (6) v
(5)
v
(5)
LVDS RSDS and mini-LVDS (7) LVPECL (8)
Differential Differential Differential
v
v v
v
v v
v v
v
v
Notes to Table 10-1:
(1) (2) (3)
(4) (5) (6) (7) (8)
These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs. PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and bottom I/O pins. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and SSTL inputs and only decode one of them. This I/O standard is not supported on these I/O pins. This I/O standard is only supported on the dedicated clock pins. PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II. mini-LVDS and RSDS are only supported on output pins. LVPECL is only supported on clock inputs.
www..com
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVTTL standard defines the DC interface parameters for digital circuits operating from a 3.0-/3.3-V power supply and driving or being driven by LVTTL-compatible devices. The LVTTL input standard specifies a wider input voltage range of - 0.3 V VI 3.9 V. Altera recommends an input voltage range of - 0.5 V VI 4.1 V.
Altera Corporation November 2004
Preliminary
10-3 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVCMOS standard defines the DC interface parameters for digital circuits operating from a 3.0- or 3.3-V power supply and driving or being driven by LVCMOS-compatible devices. The LVCMOS standard specifies the same input voltage requirements as LVTTL (- 0.3 V VI 3.9 V). The output buffer drives to the rail to meet the minimum high-level output voltage requirements. The 3.3-V I/O standard does not require input reference voltages or board terminations. Cyclone II devices support both input and output levels specified by the 3.3-V LVCMOS I/O standard.
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus Specification Revision 3.0)
The PCI local bus specification is used for applications that interface to the PCI local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The conventional PCI specification revision 3.0 defines the PCI hardware environment including the protocol, electrical, mechanical, and configuration specifications for the PCI devices and expansion boards. This standard requires a 3.3-V VCCIO. The 3.3-V PCI standard does not require input reference voltages or board terminations. The side (left and right) I/O banks on all Cyclone II devices are fully compliant with the 3.3V PCI Local Bus Specification Revision 3.0 and meet 32-bit/66 MHz operating frequency and timing requirements. Table 10-2 lists the specific Cyclone II devices that support 64- and 32-bit PCI at 66 MHz.
www..com
Table 10-2. Cyclone II 66-MHz PCI Support (Part 1 of 2) -6 & -7 Speed Grades Device
EP2C5
Package 64 Bits
144-pin TQFP 208-pin PQFP
32 Bits v v
EP2C8
144-pin TQFP 208-pin PQFP 256-pin FineLine BGA(R)
v
10-4 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Table 10-2. Cyclone II 66-MHz PCI Support (Part 2 of 2) -6 & -7 Speed Grades Device
EP2C20
Package 64 Bits
256-pin FineLine BGA 484-pin FineLine BGA
32 Bits v
v v v v v v v
v v v v v v v
EP2C35
484-pin FineLine BGA 672-pin FineLine BGA
EP2C50
484-pin FineLine BGA 672-pin FineLine BGA
EP2C70
672-pin FineLine BGA 896-pin FineLine BGA
Table 10-3 lists the specific Cyclone II devices that support 64-bit and 32-bit PCI at 33 MHz.
www..com
Device Package 64 Bits
EP2C5 144-pin TQFP 208-pin PQFP EP2C8 144-pin TQFP 208-pin PQFP 256-pin FineLine BGA EP2C20 256-pin FineLine BGA 484-pin FineLine BGA EP2C35 484-pin FineLine BGA 672-pin FineLine BGA EP2C50 484-pin FineLine BGA 672-pin FineLine BGA EP2C70 672-pin FineLine BGA 896-pin FineLine BGA
Table 10-3. Cyclone II 33-MHz PCI Support
-6, -7 & -8 Speed Grades 32 Bits v v v v v v v v v v v v v v v v v v
Altera Corporation November 2004
Preliminary
10-5 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
3.3-V PCI-X
The 3.3-V PCI-X I/O standard is formulated under PCI-X Local Bus Specification Revision 1.0 developed by the PCI SIG. The PCI-X 1.0 standard is used for applications that interface to the PCI local bus. The standard enables the design of systems and devices that operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. By using the PCI-X 1.0 standard, devices can be designed to meet PCI-X 1.0 requirements and operate as conventional 33- and 66-MHz PCI devices when installed in those systems. This standard requires 3.3-V VCCIO. Cyclone II devices are fully compliant with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133 MHz operating frequency and timing requirements. The 3.3-V PCI-X standard does not require input reference voltages or board terminations. Cyclone II devices support both input and output levels operation for horizontal I/O banks.
2.5-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5)
www..com

The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V devices. The input and output voltage requirements are: The 2.5-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 3.0 V. The normal range minimum high-level output voltage requirement (VOH) is 2.1 V. The wide range minimum VOH is VCCIO - 0.2 V.
The 2.5-V standard does not require input reference voltages or board terminations. Cyclone II devices support input and output levels for both 2.5-V LVTTL ranges.
10-6 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
2.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5)
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V parts. The input and output voltage ranges are:

The 2.5-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 3.0 V. The normal range minimum VOH requirement is 2.1 V. The wide range minimum VOH requirement is VCCIO - 0.2 V.
The 2.5-V standard does not require input reference voltages or board terminations. Cyclone II devices support input and output levels for both 2.5-V LVCMOS ranges.
SSTL-2 Class I & II (EIA/JEDEC Standard JESD8-9A)
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for applications such as high-speed double data rate (DDR) SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves operations in conditions where a bus must be isolated from large stubs. The SSTL-2 standard specifies an input voltage range of - 0.3 V VI VCCIO + 0.3 V. SSTL-2 requires a VREF value of 1.25 V and a VTT value of 1.25 V connected to the termination resistors (see Figures 10-1 and 10-2). Figure 10-1. SSTL-2 Class I Termination
VTT = 1.25 V
www..com
Output Buffer
50 25 Z = 50 VREF = 1.25 V
Input Buffer
Altera Corporation November 2004
Preliminary
10-7 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
Figure 10-2. SSTL-2 Class II Termination
VTT = 1.25 V VTT = 1.25 V 50
Output Buffer
50 25 Z = 50 VREF = 1.25 V
Input Buffer
Cyclone II devices support both input and output SSTL-2 class I and II levels.
Pseudo-Differential SSTL-2
The differential SSTL-2 I/O standard (EIA/JEDEC standard JESD8-9A) is a 2.5-V standard used for applications such as high-speed DDR SDRAM clock interfaces. This standard supports differential signals in systems using the SSTL-2 standard and supplements the SSTL-2 standard for differential clocks. The differential SSTL-2 standard specifies an input voltage range of - 0.3 V VI VCCIO + 0.3 V. The differential SSTL-2 standard does not require an input reference voltage. See Figures 10-3 and 10-4 for details on differential SSTL-2 terminations. Cyclone II devices do not support true differential SSTL-2 standards. Cyclone II devices support pseudo-differential SSTL-2 outputs for PLL_OUT pins and pseudo-differential SSTL-2 inputs for clock pins. Pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. See Table 10-1 on page 10-2 for information about pseudo-differential SSTL.
www..com
Figure 10-3. SSTL-2 Class I Differential Termination
VTT = 1.25 V VTT = 1.25 V
Differential Transmitter 25
50
50
Differential Receiver
Z0 = 50 25 Z0 = 50
10-8 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Figure 10-4. SSTL-2 Class II Differential Termination
VTT = 1.25 V VTT = 1.25 V VTT = 1.25 V VTT = 1.25 V
Differential Transmitter
50 25
50
50
50
Differential Receiver
Z0 = 50 25 Z0 = 50
1.8-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7)
The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V parts. The input and output voltage ranges are:

www..com
The 1.8-V normal and wide range input standards specify an input voltage range of - 0.3 V x VI 2.25 V. The normal range minimum VOH requirement is VCCIO - 0.45 V. The wide range minimum VOH requirement is VCCIO - 0.2 V.
The 1.8-V standard does not require input reference voltages or board terminations. Cyclone II devices support input and output levels for both normal and wide 1.8-V LVTTL ranges.
1.8-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7)
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V parts. The input and output voltage ranges are:

The 1.8-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 2.25 V. The normal range minimum VOH requirement is VCCIO - 0.45 V. The wide range minimum VOH requirement is VCCIO - 0.2 V.
Altera Corporation November 2004
Preliminary
10-9 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
The 1.8-V standard does not require input reference voltages or board terminations. Cyclone II devices support input and output levels for both normal and wide 1.8-V LVCMOS ranges.
SSTL-18 Class I & II
The 1.8-V SSTL-18 standard is formulated under JEDEC Standard, JESD815: Stub Series Terminated Logic for 1.8V (SSTL-18). The SSTL-18 I/O standard is a 1.8-V memory bus standard used for applications such as high-speed DDR2 SDRAM interfaces. This standard is similar to SSTL-2 and defines input and output specifications for devices that are designed to operate in the SSTL-18 logic switching range 0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT, with the termination resistors connected to both. There are no class definitions for the SSTL-18 standard in the JEDEC specification. The specification of this I/O standard is based on an environment that consists of both series and parallel terminating resistors. Altera provides solutions to two derived applications in JEDEC specification and names them class I and class II to be consistent with other SSTL standards. Figures 10-5 and 10-6 show SSTL-18 class I and II termination, respectively. Cyclone II devices support both input and output levels.
www..com
Figure 10-5. 1.8-V SSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 25 Z = 50 VREF = 0.9 V
Input Buffer
Figure 10-6. 1.8-V SSTL Class II Termination
VTT = 0.9 V VTT = 0.9 V 50
Output Buffer
50 25 Z = 50 VREF = 0.9 V
Input Buffer
10-10 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
1.8-V HSTL Class I & II
The HSTL standard is a technology independent I/O standard developed by JEDEC to provide voltage scalability. It is used for applications designed to operate in the 0.0- to 1.8-V HSTL logic switching range such as quad data rate (QDR) memory clock interfaces. Although JEDEC specifies a maximum VCCIO value of 1.6 V, there are various memory chip vendors with HSTL standards that require a VCCIO of 1.8 V. Cyclone II devices support interfaces with VCCIO of 1.8 V for HSTL. Figures 10-7 and 10-8 show the nominal VREF and VTT required to track the higher value of VCCIO. The value of VREF is selected to provide optimum noise margin in the system. Cyclone II devices support both input and output levels of operation. Figure 10-7. 1.8-V HSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 Z = 50 VREF = 0.9 V
Input Buffer
www..com
Figure 10-8. 1.8-V HSTL Class II Termination
VTT = 0.9 V VTT = 0.9 V 50 Z = 50 VREF = 0.9 V
Output Buffer
50
Input Buffer
Pseudo-Differential SSTL-18 Class I & Differential SSTL-18 Class II
The 1.8-V differential SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8V (SSTL-18).
Altera Corporation November 2004
Preliminary
10-11 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
The differential SSTL-18 I/O standard is a 1.8-V standard used for applications such as high-speed DDR2 SDRAM interfaces. This standard supports differential signals in systems using the SSTL-18 standard and supplements the SSTL-18 standard for differential clocks. See Figures 10-9 and 10-10 for details on differential SSTL-18 termination. Cyclone II devices do not support true differential SSTL-18 standards. Cyclone II devices support pseudo-differential SSTL-18 outputs for PLL_OUT pins and pseudo-differential SSTL-18 inputs for clock pins. Pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. See Table 10-1 on page 10-2 for information about pseudo-differential SSTL. Figure 10-9. Differential SSTL-18 Class I Termination
VTT = 0.9 V VTT = 0.9 V
Differential Transmitter 25
50
50
Differential Receiver
Z0 = 50
www..com
25 Z0 = 50
Figure 10-10. Differential SSTL-18 Class II Termination
VTT = 0.9 V VTT = 0.9 V VTT = 0.9 V VTT = 0.9 V
Differential Transmitter
50 25
50
50
50
Differential Receiver
Z0 = 50 25 Z0 = 50
10-12 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
1.8-V Pseudo-Differential HSTL Class I & II
The 1.8-V differential HSTL specification is the same as the 1.8-V singleended HSTL specification. It is used for applications designed to operate in the 0.0 to 1.8-V HSTL logic switching range such as QDR memory clock interfaces. Cyclone II devices support both input and output levels. See Figures 10-11 and 10-12 for details on 1.8-V differential HSTL termination. Cyclone II devices do not support true 1.8-V differential HSTL standards. Cyclone II devices support pseudo-differential HSTL outputs for PLL_OUT pins and pseudo-differential HSTL inputs for clock pins. Pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. See Table 10-1 on page 10-2 for information about pseudo-differential HSTL. Figure 10-11. 1.8-V Differential HSTL Class I Termination
VTT = 0.9 V VTT = 0.9 V
Differential Transmitter Z0 = 50
50
50
Differential Receiver
www..com
Z0 = 50
Figure 10-12. 1.8-V Differential HSTL Class II Termination
VTT = 0.9 V VTT = 0.9 V VTT = 0.9 V VTT = 0.9 V
Differential Transmitter
50
50
50
50
Differential Receiver
Z0 = 50
Z0 = 50
Altera Corporation November 2004
Preliminary
10-13 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
1.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard JESD8-11)
The 1.5-V I/O standard is used for 1.5-V applications. This standard defines the DC interface parameters for high-speed, low-voltage, nonterminated digital circuits driving or being driven by other 1.5-V devices. The input and output voltage ranges are:

The 1.5-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 1.9 V. The normal range minimum VOH requirement is 1.05 V. The wide range minimum VOH requirement is VCCIO - 0.2 V.
The 1.5-V standard does not require input reference voltages or board terminations. Cyclone II devices support input and output levels for both normal and wide 1.5-V LVCMOS ranges.
1.5-V HSTL Class I & II
The 1.5-V HSTL standard is formulated under EIA/JEDEC Standard, EIA/JESD8-6: A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits.
www..com
The 1.5-V HSTL I/O standard is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard defines single-ended input and output specifications for all HSTLcompliant digital integrated circuits. The 1.5-V HSTL I/O standard in Cyclone II devices is compatible with the 1.8-V HSTL I/O standard in APEXTM 20KE, APEX 20KC, Stratix(R) II, Stratix GX, Stratix, and in Cyclone II devices themselves because the input and output voltage thresholds are compatible. See Figures 10-13 and 10-14. Cyclone II devices support both input and output levels with VREF and VTT. Figure 10-13. 1.5-V HSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Z = 50 VREF = 0.75 V
Input Buffer
10-14 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Figure 10-14. 1.5-V HSTL Class II Termination
VTT = 0.75 V VTT = 0.75 V 50 Z = 50 VREF = 0.75 V
Output Buffer
50
Input Buffer
1.5-V Pseudo-Differential HSTL Class I & II
The 1.5-V differential HSTL standard is formulated under EIA/JEDEC Standard, EIA/JESD8-6: A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits. The 1.5-V differential HSTL specification is the same as the 1.5-V singleended HSTL specification. It is used for applications designed to operate in the 0.0- to 1.5-V HSTL logic switching range, such as QDR memory clock interfaces. Cyclone II devices support both input and output levels. See Figures 10-15 and 10-16 for details on the 1.5-V differential HSTL termination. Cyclone II devices do not support true 1.5-V differential HSTL standards. Cyclone II devices support pseudo-differential HSTL outputs for PLL_OUT pins and pseudo-differential HSTL inputs for clock pins. Pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. See Table 10-1 on page 10-2 for information about pseudo-differential HSTL.
www..com
Figure 10-15. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V VTT = 0.75 V
Differential Transmitter Z0 = 50
50
50
Differential Receiver
Z0 = 50
Altera Corporation November 2004
Preliminary
10-15 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Supported I/O Standards
Figure 10-16. 1.5-V Differential HSTL Class II Termination
VTT = 0.75 V VTT = 0.75 V VTT = 0.75 V VTT = 0.75 V
Differential Transmitter
50
50
50
50
Differential Receiver
Z0 = 50
Z0 = 50
LVDS, RSDS & mini-LVDS
The LVDS standard is formulated under ANSI/TIA/EIA Standard, ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage Differential Signaling Interface Circuits.
www..com
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers must be capable of operating at maximum data signaling rates of 655 megabits per second (Mbps). However, devices can operate at slower speeds if needed. Cyclone II devices are capable of running at a maximum data rate of 805 Mbps for input and 622 Mbps for output and still meet the ANSI/TIA/EIA-644 standard, with the following exceptions:

The maximum differential output voltage (VOD) is increased to 600 mV. The input voltage range is from 0 to 1.85 V for data rates less than 700 Mbps. The input voltage range is reduced to 1.0 to 1.6 V for data rates above 700 Mbps.
Because of the low voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than complementary metal-oxide semiconductor (CMOS), transistor-totransistor logic (TTL), and positive (or pseudo) emitter coupled logic (PECL). This low EMI makes LVDS ideal for applications with low EMI requirements or noise immunity requirements. The LVDS standard does not require an input reference voltage. However, it does require a
10-16 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
termination resistor of 90 to 110 between the two signals at the input buffer. Cyclone II devices support true differential LVDS inputs and outputs.
f
LVDS outputs on Cyclone II need external resistor network to work properly. See the High Speed Differential Interfaces in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook for more information. For reduced swing differential signaling (RSDS), VOD ranges from 100 to 600 mV. For mini-LVDS, VOD ranges from 300 to 600 mV. The differential termination resistor value ranges from 95 to 105 for both RSDS and mini-LVDS. Cyclone II devices support RSDS/mini-LVDS outputs only.
Differential LVPECL
The low voltage positive (or pseudo) emitter coupled logic (LVPECL) standard is a differential interface standard requiring a 3.3-V VCCIO. The standard is used in applications involving video graphics, telecommunications, data communications, and clock distribution. The high-speed, low-voltage swing LVPECL I/O standard uses a positive power supply and is similar to LVDS. However, LVPECL has a larger differential output voltage swing than LVDS. The LVPECL standard does not require an input reference voltage, but it does require an external 100- termination resistor between the two signals at the input buffer. Figures 10-17 and 10-18 show two alternate termination schemes for LVPECL. LVPECL input standard is supported at the clock input pins on Cyclone II devices. LVPECL output standard is not supported. Figure 10-17. LVPECL DC Coupled Termination
Output Buffer
Z = 50 100 Z = 50
www..com
Input Buffer
Altera Corporation November 2004
Preliminary
10-17 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Cyclone II I/O Banks
Figure 10-18. LVPECL AC Coupled Termination
VCCIO VCCIO Z = 50 100 10 to 100 nF Z = 50 R2 R2 R1 R1
Output Buffer
10 to 100 nF
Input Buffer
Cyclone II I/O Banks
The I/O pins on Cyclone II devices are grouped together into I/O banks, and each bank has a separate power bus. This permits designers to select the preferred I/O standard for a given bank enabling tremendous flexibility in the Cyclone II device's I/O support. EP2C5 and EP2C8 devices support four I/O banks. EP2C20, EP2C35, EP2C50, and EP2C70 devices support eight I/O banks. Each device I/O pin is associated with one of these specific, numbered I/O banks (see Figures 10-19 and 10-20). To accommodate voltage-referenced I/O standards, each Cyclone II I/O bank has separate VREF bus. Each bank in EP2C5, EP2C8, EP2C20, EP2C35, and EP2C50 devices supports two VREF pins and each bank in EP2C70 devices supports four VREF pins. In the event these pins are not used as VREF pins, they may be used as regular I/O pins. However, they are expected to have slightly higher pin capacitance than other user I/O pins when used with regular user I/O pins.
www..com
10-18 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Figure 10-19. EP2C5 & EP2C8 Device I/O Banks Notes (1), (2)
Regular I/O Bank
2
Individual Power Bus
Regular I/O Bank
1
3
Regular I/O Bank
www..com
4 Regular I/O Bank
Notes to Figure 10-19:
(1) (2) This is a top view of the silicon die. This is a graphic representation only. See the pin list and the Quartus II software for exact pin locations.
Altera Corporation November 2004
Preliminary
10-19 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Cyclone II I/O Banks
Figure 10-20. EP2C20, EP2C35, EP2C50 & EP2C70 Device I/O Banks Notes (1), (2)
Regular I/O Bank 3 Regular I/O Bank
4
Individual Power Bus
Regular I/O Bank 2 5 Regular I/O Bank
Regular I/O Bank
1
6
Regular I/O Bank
www..com
Regular I/O Bank Regular I/O Bank
8
7
Notes to Figure 10-20:
(1) (2) This is a top view of the silicon die. This is a graphic representation only. See the pin list and the Quartus II software for exact pin locations.
10-20 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Additionally, each Cyclone II I/O bank has its own VCCIO pins. Any single I/O bank can only support one VCCIO setting from among 1.5, 1.8, 2.5 or 3.3 V. Although there can only be one VCCIO voltage per I/O bank, Cyclone II devices permit additional input signaling capabilities, as shown in Table 10-4.
Table 10-4. Acceptable Input Levels for LVTTL & LVCMOS Acceptable Input Levels (V) Bank VCCIO (V)
3.3 2.5 1.8 1.5 Notes to Table 10-4:
(1) Because the input level will not drive to the rail, the input buffer does not completely shut off, and the I/O current will be slightly higher than the default value. These input values overdrive the input buffer, so the pin leakage current will be slightly higher than the default value.
3.3 v v v (2) v (2)
2.5 v (1) v v (2) v (2)
1.8
1.5
v v
v (1) v
(2)
www..com
Any number of supported single-ended or differential standards can be simultaneously supported in a single I/O bank as long as they use compatible VCCIO levels for input and output pins. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs, 2.5-V LVDS-compatible inputs and outputs, and 3.3-V LVCMOS inputs only. Voltage-referenced standards can be supported in an I/O bank using any number of single-ended or differential standards as long as they use the same VREF and a compatible VCCIO value. For example, if you choose to implement both SSTL-2 and SSTL-18 in your Cyclone II device, I/O pins using these standards--because they require different VREF values--must be in different banks from each other. However, the same I/O bank can support SSTL-2 and 2.5-V LVCMOS with the VCCIO set to 2.5 V and the VREF set to 1.25 V.
f
See "Pad Placement & DC Guidelines" on page 10-26 for more information. Table 10-5 shows I/O standards supported when a pin is used as a regular I/O pin in the I/O banks of Cyclone II devices.
Altera Corporation November 2004
Preliminary
10-21 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Cyclone II I/O Banks
Table 10-5. Cyclone II Regular I/O Standards Support I/O Banks for EP2C20, EP2C35, EP2C50 & EP2C70 Devices 1
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I
I/O Standard
I/O Banks for EP2C5 & EP2C8 Devices 1 v v v v v v v 2 v v v v v 3 v v v v v v v v v v v v v v
(2) (2) (2) (2)
2 v v v v v v v v v v
(1)
3 v v v v v
4 v v v v v
5 v v v v v v v
6 v v v v v v v v v v
(1)
7 v v v v v
8 v v v v v
4 v v v v v
v v v v v v v v v v
(1)
v v v v v v v
(2) (2) (2) (2)
v v v v v v v
(2) (2) (2) (2)
v v v
(1)
v v v v v v v
(2) (2) (2) (2)
v v v v v v v
(2) (2) (2) (2)
v v v
(1)
v v v
(1)
v v v v v v v v
(2) (2) (2) (2)
1.8-V HSTL class II 1.5-V HSTL class I 1.5-V HSTL class II Pseudo-differential SSTL-2 Pseudo-differential SSTL-18 1.8-V pseudodifferential HSTL 1.5-V pseudodifferential HSTL LVDS
www..com
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
(1)
v
v
v
v
v
v
(1) (2) (2) (2) (2)
v
(1) (2) (2) (2) (2)
v
(1) (2) (2) (2) (2)
v
(1) (2) (2) (2) (2)
v
(1) (2) (2) (2) (2)
v
(1) (2) (2) (2) (2)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
v
(3) (4)
RSDS and mini-LVDS Differential LVPECL Notes to Table 10-5:
(1) (2) (3) (4)
These I/O banks support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs. Pseudo-differential I/O standards are only supported for clock inputs and dedicated PLL_OUT outputs. See Table 10-1 for more information. This I/O standard is only supported for outputs. This I/O standard is only supported for the clock inputs.
10-22 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Programmable Current Drive Strength
The Cyclone II device I/O standards support various output current drive settings as shown in Table 10-6. These programmable drivestrength settings are a valuable tool in helping decrease the effects of simultaneously switching outputs (SSO) in conjunction with reducing system noise. The supported settings ensure that the device driver meets the specifications for IOH and IOL of the corresponding I/O standard.
Table 10-6. Programmable Drive Strength I/O Standard
LVTTL (3.3 V)
(Part 1 of 2)
IOH/IOL Current Strength Setting (mA) Top & Bottom I/O Pins
4 8 12 16 20 24
Side I/O Pins
4 8 12 16 20 24 4 8 12
LVCMOS (3.3 V)
4 8
www..com
12 16 20 24 LVTTL and LVCMOS (2.5 V) 4 8 12 16 LVTTL and LVCMOS (1.8 V) 2 4 6 8 10 12 LVCMOS (1.5 V) 2 4 6 8
4 8
2 4 6 8 10 12 2 4 6
Altera Corporation November 2004
Preliminary
10-23 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Programmable Current Drive Strength
Table 10-6. Programmable Drive Strength I/O Standard
SSTL-2 class I
(Part 2 of 2)
IOH/IOL Current Strength Setting (mA) Top & Bottom I/O Pins
8 12
Side I/O Pins
8 12 16
SSTL-2 class II
16 20 24
SSTL-18 class I
4 6 8 10 12
4 6 8 10
SSTL-18 class II
8 16 18
N/A
www..com
6 8 10 12 HSTL-18 class II 16 18 20 HSTL-15 class I 4 6 8 10 12 HSTL-15 class II 16
HSTL-18 class I
4
4 6 8 10 12
N/A
4 6 8
N/A
These drive-strength settings are programmable on a per-pin basis using the Quartus II software.
10-24 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
I/O Termination
The majority of the Cyclone II I/O standards are single-ended, nonvoltage-referenced I/O standards and, as such, the following I/O standards do not specify a recommended termination scheme:

3.3-V LVTTL and LVCMOS 2.5-V LVTTL and LVCMOS 1.8-V LVTTL and LVCMOS 1.5-V LVCMOS 3.3-V PCI and PCI-X
Voltage-Referenced I/O Standard Termination
Voltage-referenced I/O standards require both an input reference voltage, VREF, and a termination voltage, VTT. The reference voltage of the receiving device tracks the termination voltage of the transmitting device.
f
For more information on termination for voltage-referenced I/O standards, see "Supported I/O Standards" on page 10-1.
Differential I/O Standard Termination
www..com
f
Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the bus. Cyclone II devices support differential I/O standards LVDS, RSDS, and mini-LVDS, and differential LVPECL. For more information on termination for differential I/O standards, see "Supported I/O Standards" on page 10-1.
Altera Corporation November 2004
Preliminary
10-25 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Pad Placement & DC Guidelines
I/O Driver Impedance Matching (RS) & Series Termination (RS)
Cyclone II devices support driver impedance matching to the impedance of the transmission line, typically 25 or 50 . When used with the output drivers, on-chip termination (OCT) sets the output driver impedance to 25 or 50 by choosing the driver strength. Once matching impedance is selected, driver current can not be changed. Table 10-7 provides a list of output standards that support impedance matching.
Table 10-7. Selectable I/O Drivers with Impedance Matching & Series Termination I/O Standard
3.3-V LVTTL/CMOS 2.5-V LVTTL/CMOS 1.8-V LVTTL/CMOS SSTL-2 class I SSTL-18 class I Note to Table 10-7:
(1)
Target RS ()
25 (1) 50 (1) 50 (1) 50 (1) 50 (1)
www..com
Pad Placement & DC Guidelines
These RS values are nominal values. Actual impedance will vary across process, voltage, and temperature conditions. Tolerance is pending characterization.
This section provides pad placement guidelines for the programmable I/O standards supported by Cyclone II devices and includes essential information for designing systems using the devices' selectable I/O capabilities. This section also discusses the DC limitations and guidelines. Quartus II software provides user controlled restriction relaxation options for some placement constraints. When a default restriction is relaxed by a user, the Quartus II fitter generates warnings.
f
For more information about how Quartus II software checks I/O restrictions, see the I/O Assignment Planning & Analysis chapter in the Quartus II Handbook.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply, there are restrictions on placement of single-ended I/O pads in relation to differential pads. Use the following guidelines for placing single-ended pads with respect to differential pads and for differential output pads placement in Cyclone II devices.
10-26 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
For the LVDS I/O standard:

Single-ended inputs can be no closer than four pads away from an LVDS I/O pad. Single-ended outputs can be no closer than five pads away from an LVDS I/O pad. Maximum of four 155-MHz LVDS output channels per VCCIO and ground pair. Maximum of three 311-MHz LVDS output channels per VCCIO and ground pair.
The Quartus II software only checks the first two cases. For the RSDS and mini-LVDS I/O standards:

Single-ended inputs can be no closer than four pads away from an RSDS and mini-LVDS output pad. Single-ended outputs can be no closer than five pads away from an RSDS and mini-LVDS output pad. Maximum of three 85-MHz RSDS and mini-LVDS output channels per VCCIO and ground pair.
www..com
VREF Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply and to prevent output switching noise from shifting the VREF rail, there are restrictions on the placement of single-ended voltage referenced I/Os with respect to VREF pads and VCCIO and ground pairs. Use the following guidelines for placing single-ended pads in Cyclone II devices. The Quartus II software automatically does all the calculations in this section.
The Quartus II software only checks the first two cases.
Input Pads
Each VREF pad supports up to 15 input pads on each side of the VREF pad for FineLine BGA devices. Each VREF pad supports up to 10 input pads on each side of the VREF pad for quad flat pack (QFP) devices. This is irrespective of VCCIO and ground pairs, and is guaranteed by the Cyclone II architecture.
Altera Corporation November 2004
Preliminary
10-27 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Pad Placement & DC Guidelines
Output Pads
When a voltage referenced input or bidirectional pad does not exist in a bank, there is no limit to the number of output pads that can be implemented in that bank. When a voltage referenced input exists, each VCCIO and ground pair supports nine outputs for Fineline BGA packages or five outputs for QFP packages. Any non-SSTL and non-HSTL output can be no closer than two pads away from a VREF pad to maintain acceptable noise levels. Any SSTL and HSTL output, except for pintable defined DQ and DQS outputs, can be no closer than two pads away from a VREF pad.
f
See "DDR & QDR Pads" on page 10-31 for details about guidelines for DQ and DQS pads placement.
Bidirectional Pads
Bidirectional pads must satisfy input and output guidelines simultaneously.
f
See "DDR & QDR Pads" on page 10-31 for details about guidelines for DQ and DQS pads placement. If the bidirectional pads are all controlled by the same output enable (OE) and there are no other outputs or voltage referenced inputs in the bank, then there is no case where there is a voltage referenced input is active at the same time as an output. Therefore, the output limitation does not apply. However, since the bidirectional pads are linked to the same OE, all the bidirectional pads will act as inputs at the same time. Therefore, the input limitation of 30 input pads (15 on each side of the VREF pad) for FineLine BGA packages and 20 input pads (10 on each side of the VREF pad) for QFP packages will apply.
www..com
10-28 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
If the bidirectional pads are all controlled by different OEs, and there are no other outputs or voltage referenced inputs in the bank, then there may be a case where one group of bidirectional pads is acting as inputs while another group is acting as outputs. In such cases, apply the formulas shown in Table 10-8.
Table 10-8. Input-Only Bidirectional Pad Limitation Formulas Package Type
FineLine BGA
Formula
(Total number of bidirectional pads) - (Total number of pads from the smallest group of pads controlled by an OE) 9 (per VCCIO and ground pair) (Total number of bidirectional pads) - (Total number of pads from the smallest group of pads controlled by an OE) 5 (per VCCIO and ground pair).
QFP
www..com
Consider a FineLine BGA package with four bidirectional pads controlled by the first OE, four bidirectional pads controlled by the second OE, and two bidirectional pads controlled by the third OE. If the first and second OEs are active and the third OE is inactive, there are 10 bidirectional pads, but it is safely allowable because there would be 8 or fewer outputs per VCCIO/GND pair.
When at least one additional voltage referenced input and no other outputs exist in the same VREF bank, the bidirectional pad limitation applies in addition to the input and output limitations. See the following equations: Total number of bidirectional pads + total number of input pads 30 (15 on each side of your VREF pad) for Fineline BGA packages Total number of bidirectional pads + total number of input pads 20 (10 on each side of your VREF pad) for QFP packages After applying the equation above, apply one of the equations in Table 10-9, depending on the package type.
Table 10-9. Bidirectional Pad Limitation Formulas (Where VREF Inputs Exist) Package Type
FineLine BGA QFP
Formula
(Total number of bidirectional pads) 9 (per VCCIO and ground pair) (Total number of bidirectional pads) 5 (per VCCIO and ground pair)
Altera Corporation November 2004
Preliminary
10-29 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Pad Placement & DC Guidelines
When at least one additional output exists but no voltage referenced inputs exist, apply the appropriate formula from Table 10-10.
Table 10-10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist) Package Type
FineLine BGA
Formula
(Total number of bidirectional pads) + (Total number of additional output pads) - (Total number of pads from the smallest group of pads controlled by an OE) 9 (per VCCIO and ground pair) (Total number of bidirectional pads) + (Total number of additional output pads) - (Total number of pads from the smallest group of pads controlled by an OE) 5 (per VCCIO and ground pair)
QFP
When additional voltage referenced inputs and other outputs exist in the same VREF bank, the bidirectional pad limitation must again simultaneously adhere to the input and output limitations. As such, the following rules apply:
www..com
Total number of bidirectional pads + total number of input pads 30 (15 on each side of your VREF pad) for Fineline BGA packages
Total number of bidirectional pads + total number of input pads 20 (10 on each side of your VREF pad) for QFP packages After applying the equation above, apply one of the equations in Table 10-11, depending on the package type.
Table 10-11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs) Package Type
FineLine BGA QFP
Formula
(Total number of bidirectional pads) + (Total number of output pads) 9 (per VCCIO/GND pair) Total number of bidirectional pads + Total number of output pads 5 (per VCCIO/GND pair)
Each I/O bank can only be set to a single VCCIO voltage level and a single VREF voltage level at a given time. Pins of different I/O standards can share the bank if they have compatible VCCIO values (see Table 10-4 for more details) and compatible VREF voltage levels.
10-30 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
DDR & QDR Pads
For dedicated DQ and DQS pads on a DDR interface, DQ pads have to be on the same power bank as DQS pads. With the DDR and DDR2 memory interfaces, a VCCIO and ground pair can have a maximum of five DQ pads. For a QDR interface, D is the QDR output and Q is the QDR input. D pads and Q pads have to be on the same power bank as CQ. With the QDR and QDRII memory interfaces, a VCCIO and ground pair can have a maximum of five D and Q pads. By default, the Quartus II software assigns D and Q pads as regular I/O pins. If you do not specify the function of a D or Q pad in the Quartus II software, the software will set them as regular I/O pins. If this occurs, Cyclone II QDR and QDRII performance is not guaranteed.
DC Guidelines
There is a current limit of 240 mA per eight consecutive output top and bottom pins per power pair, as shown by the following equation:
www..com
There is a current limit of 240 mA per 12 consecutive output side (left and right) pins per power pair, as shown by the following equation: pin+11 IPIN < 240mA per power pair pin In all cases listed above, the Quartus II software generates an error message for illegally placed pads.
pin+7 IPIN < 240mA per power pair pin
Altera Corporation November 2004
Preliminary
10-31 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Pad Placement & DC Guidelines
Table 10-12 shows the I/O standard DC current specification.
Table 10-12. Cyclone II I/O Standard DC Current Specification (Preliminary) (Part 1 of 2) I/O Standard Top & Bottom Banks
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X SSTL-2 class I SSTL-2 class II SSTL-18 class I SSTL-18 class II 1.8-V HSTL class I (1) (1) (1) (1) (1) Not supported Not supported 12 (2) 24 (2) 12 (2) 8 (2) 12 (2)
IPIN (mA) Side Banks
(1) (1) (1) (1) (1) 1.5 1.5 12 (2) 20 (2) 12 (2) Not supported 12 (2)
1.8-V HSTL class II 1.5-V HSTL class I
www..com
20 (2) 12 (2) 10 (2) 18 (2) 8.1 (4) 16.4 (4) 6.7 (4) 13.4 (4) 8 (4) 16 (4) 8 (4)
Not supported
1.5-V HSTL class II Differential SSTL-2 class I (3) Differential SSTL-2 class II (3) Differential SSTL-18 class I (3) Differential SSTL-18 class II (3) 1.8-V differential HSTL class I (3) 1.8-V differential HSTL class II (3) 1.5-V differential HSTL class I (3)
Not supported
10-32 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Selectable I/O Standards in Cyclone II Devices
Table 10-12. Cyclone II I/O Standard DC Current Specification (Preliminary) (Part 2 of 2) I/O Standard Top & Bottom Banks
1.5-V differential HSTL class II (3) LVDS, RSDS and mini-LVDS Notes to Table 10-12:
(1) The DC power specification of each I/O standard depends on the current sourcing and sinking capabilities of the I/O buffer programmed with that standard, as well as the load being driven. LVTTL and LVCMOS, and 2.5-, 1.8-, and 1.5-V outputs are not included in the static power calculations because they normally do not have resistor loads in real applications. The voltage swing is rail-to-rail with capacitive load only. There is no DC current in the system. This IPIN value represents the DC current specification for the default current strength of the I/O standard. The IPIN varies with programmable drive strength and is the same as the drive strength as set in Quartus II software. See the Cyclone II Architecture chapter in Volume 1 of the Cyclone II Device Handbook for more information on the programmable drive strength feature of voltage referenced I/O standards. The current value obtained for differential HSTL and differential SSTL standards is per pin and not per differential pair, as opposed to the per-pair current value of LVDS standard. This I/O standard is only supported for clock input pins and PLL_OUT pins.
IPIN (mA) Side Banks
16 (4) 12 12
(2)
(3) (4)
www..com
Conclusion
Table 10-12 only shows the limit on the static power consumed by an I/O standard. The amount of total power used at any moment could be much higher, and is based on the switching activities. Cyclone II device I/O capabilities enable system designers to keep pace with increasing design complexity utilizing a low-cost FPGA device family. Support for I/O standards including SSTL and LVDS compatibility allow Cyclone II devices to fit into a wide variety of applications. The Quartus II software makes it easy to use these I/O standards in Cyclone II device designs. After design compilation, the software also provides clear, visual representations of pads and pins and the selected I/O standards. Taking advantage of the support of these I/O standards in Cyclone II devices will allow you to lower your design costs without compromising design flexibility or complexity. For more information on Cyclone II devices, see the following resources:

More Information
Section I, Cyclone II Device Family Data Sheet of the Cyclone II Device Handbook AN 75: High-Speed Board Designs
Altera Corporation November 2004
Preliminary
10-33 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
References
References
For more information on the I/O standards referred to in this document, see the following sources:

www..com
Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9A, Electronic Industries Association, December 2000. 1.5-V +/- 0.1-V (Normal Range) and 0.9-V - 1.6-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-11, Electronic Industries Association, October 2000. 1.8-V +/- 0.15-V (Normal Range) and 1.2-V - 1.95-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-7, Electronic Industries Association, February 1997. 2.5-V +/- 0.2-V (Normal Range) and 1.8-V to 2.7-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-5, Electronic Industries Association, October 1995. Interface Standard for Nominal 3-V/ 3.3-V Supply Digital Integrated Circuits, JESD8-B, Electronic Industries Association, September 1999. PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 1998. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunications Industry/Electronic Industries Association, October 1995.
10-34 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
Chapter 11. High-Speed Differential Interfaces in Cyclone II Devices
CII51011-1.1
Introduction
From high-speed backplane applications to high-end switch boxes, lowvoltage differential signaling (LVDS) is the technology of choice. LVDS is a low-voltage differential signaling standard, allowing higher noise immunity than single-ended I/O technologies. Its low-voltage swing allows for high-speed data transfers, low power consumption, and reduced electromagnetic interference (EMI). LVDS I/O signaling is a data interface standard defined in the TIA/EIA-644 and IEEE Std. 1596.3 specifications. The reduced swing differential signaling (RSDS) and mini-LVDS standards are derivatives of the LVDS standard. The RSDS and mini-LVDS I/O standards are similar in electrical characteristics to LVDS, but have a smaller voltage swing and therefore provide increased power benefits and reduced EMI. National Semiconductor Corporation and Texas Instruments introduced the RSDS and mini-LVDS specifications, respectively. Currently many designers use these specifications for flat panel display links between the controller and the drivers that drive display column drivers. CycloneTM II devices support the RSDS and mini-LVDS I/O standards at speeds up to 170 megabits per second (Mbps) at the transmitter. For RSDS and mini-LVDS, the maximum internal clock frequency is 85 MHz.
www..com
Altera(R) Cyclone II devices can transmit and receive data through LVDS signals at a data rate of up to 622 Mbps and 805 Mbps, respectively. For the LVDS transmitter and receiver, the Cyclone II device's input and output pins support serialization and deserialization through internal logic. This chapter describes how to use Cyclone II I/O pins for differential signaling and contains the following topics:

Cyclone II high-speed I/O banks Cyclone II high-speed I/O interface LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL I/O standards support in Cyclone II devices High-speed I/O timing in Cyclone II devices Design guidelines
Altera Corporation November 2004
11-1 Preliminary
www..com www..com 4U
www..com
Cyclone II High-Speed I/O Banks
Cyclone II HighSpeed I/O Banks
Cyclone II device I/O banks are shown in Figures 11-1 and 11-2. The EP2C5 and EP2C8 devices offer four I/O banks and EP2C20, EP2C35, EP2C50, and EP2C70 devices offer eight I/O banks. A subset of pins in each I/O bank (on both rows and columns) support the high-speed I/O interface. Cyclone II pin tables list the pins that support the high-speed I/O interface.
Figure 11-1. I/O Banks in EP2C5 & EP2C8 Devices
I/O Bank 2 Also Supports the SSTL-18 Class II, HSTL-18 Class II, & HSTL-15 Class II I/O Standards I/O Bank 2
I/O Bank 1 Also Supports the 3.3-V PCI & PCI-X I/O Standards
www..com
I/O Bank 1 I/O Bank 3 Individual Power Bus
All I/O Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS RSDS mini-LVDS LVPECL SSTL-2 Class I and II SSTL-18 Class I HSTL-18 Class I HSTL-15 Class I Differential SSTL-2 Differential SSTL-18 Differential HSTL-18 Differential HSTL-15
I/O Bank 3 Also Supports the 3.3-V PCI & PCI-X I/O Standards
I/O Bank 4 I/O Bank 4 Also Supports the SSTL-18 Class II, HSTL-18 Class II, & HSTL-15 Class II I/O Standards
11-2 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
Figure 11-2. I/O Banks in EP2C20, EP2C35, EP2C50 & EP2C70 Devices
I/O Banks 3 & 4 Also Support the SSTL-18 Class II, HSTL-18 Class II, & HSTL-15 Class II I/O Standards I/O Bank 3 I/O Bank 4
Individual Power Bus I/O Bank 2 All I/O Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS RSDS mini-LVDS LVPECL SSTL-2 Class I and II SSTL-18 Class I HSTL-18 Class I HSTL-15 Class I Differential SSTL-2 Differential SSTL-18 Differential HSTL-18 Differential HSTL-15 I/O Bank 5
I/O Banks 1 & 2 Also Support the 3.3-V PCI & PCI-X I/O Standards
I/O Banks 5 & 6 Also Support the 3.3-V PCI & PCI-X I/O Standards
I/O Bank 1
I/O Bank 6
www..com
Regular I/O Block Bank 8 Regular I/O Block Bank 7 I/O Banks 7 & 8 Also Support the SSTL-18 Class II, HSTL-18 Class II, & HSTL-15 Class II I/O Standards
Cyclone II High-Speed I/O Interface
Cyclone II devices provide a multi-protocol interface that allows communication between a variety of I/O standards, including LVDS, LVPECL, RSDS, mini-LVDS, differential HSTL, and differential SSTL. This feature makes the Cyclone II device family ideal for applications that require multiple I/O standards, such as protocol translation.
Altera Corporation November 2004
Preliminary
11-3 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
I/O Standards Support
You can use I/O pins and internal logic to implement a high-speed I/O receiver and transmitter in Cyclone II devices. Cyclone II devices do not contain dedicated serialization or deserialization circuitry. Therefore, shift registers, internal global phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data.
I/O Standards Support
This section provides information on the I/O standards that Cyclone II devices support.
LVDS Standard Support in Cyclone II Devices
The LVDS I/O standard is a high-speed, low-voltage swing, low power, and general purpose I/O interface standard. The Cyclone II device meets the ANSI/TIA/EIA-644 standard, with the following exceptions:

The maximum VOD is increased to 600 mV. The input voltage range is reduced to a minimum of 0.5 V and a maximum of 1.85 V for data rates less than 700 Mbps. The input voltage range is reduced to a minimum of 1.0 V and a maximum of 1.6 V for data rates above 700 Mbps.
www..com
I/O banks on all four sides of the Cyclone II device support LVDS channels. See the pin tables on the Altera web site for the number of LVDS channels supported throughout different family members. Cyclone II LVDS receivers (input) support a data rate of up to 805 Mbps while LVDS transmitters (output) support up to 622 Mbps. The maximum internal clock frequency for a receiver is 402.5 MHz. The maximum clock frequency for a transmitter is 311 MHz. The maximum data rate of 805 Mbps is only achieved when DDIO registers are used. The LVDS standard does not require an input reference voltage; however, it does require a 100- termination resistor between the two signals at the input buffer. Table 11-1 shows LVDS I/O specifications.
Table 11-1. LVDS I/O Specifications (Part 1 of 2) Symbol
VCCINT VCCIO VOD VOD VOS
Parameter
Supply voltage I/O supply voltage
Condition
Min
1.15 2.375 247
Typ
1.2 2.5
Max
1.25 2.625 600 50
Units
V V mv mv V
Differential output voltage RL = 100 Change in VOD between H and L Output offset voltage RL = 100 RL = 100
1.125
1.25
1.375
11-4 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
Table 11-1. LVDS I/O Specifications (Part 2 of 2) Symbol
VOS VIN
Parameter
Change in VOS between H and L Receiver input voltage range
Condition
RL = 100 Data rate 700 Mbps Data rate > 700 Mbps
Min
Typ
Max
50
Units
mv V V
0.5 1.0 90 100
1.85 1.6 110
RL
Receiver differential input resistor
LVDS Receiver & Transmitter
Figure 11-3 shows a simple point-to-point LVDS application where the source of the data is an LVDS transmitter. These LVDS signals are typically transmitted over a pair of printed circuit board (PCB) traces, but a combination of a PCB trace, connectors, and cables is a common application setup. Figure 11-3. Typical LVDS Application
www..com
Cyclone II Device txout + rxin + 100 txout rxin txout Cyclone II Logic Array txout + 120 120 rxin + 170 rxin 100 Receiving Device Input Buffer Output Buffer
Transmitting Device
Figures 11-4 and 11-5 show the signaling levels for LVDS receiver inputs and transmitter outputs, respectively.
Altera Corporation November 2004
Preliminary
11-5 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
I/O Standards Support
Figure 11-4. Receiver Input Waveforms for the LVDS Differential I/O Standard
Single-Ended Waveform Positive Channel (p) = VOH VID Negative Channel (n) = VOL VOS Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VID 0V VID VID p - n (1)
Note to Figure 11-4:
(1) The p - n waveform is a function of the positive channel (p) and the negative channel (n).
Figure 11-5. Transmitter Output Waveform for the LVDS Differential I/O Standard
Single-Ended Waveform
www..com
Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VOS Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VOD 0V VOD p - n (1)
Note to Figure 11-5:
(1) The p - n waveform is a function of the positive channel (p) and the negative channel (n).
11-6 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
RSDS I/O Standard Support in Cyclone II Devices
The RSDS specification is used in chip-to-chip applications between the timing controller and the column drivers on display panels. Cyclone II devices meet the National Semiconductor Corporation RSDS Interface Specification and support the RSDS output standard. Table 11-2 shows the RSDS electrical characteristics for Cyclone II devices.
Table 11-2. RSDS Electrical Characteristics for Cyclone II Devices Symbol
VC C I O VOD (1) VOS (2) Tr/Tf
(1) (2)
Parameter
Output supply voltage Differential output voltage Output offset voltage Transition time
Condition
RL = 100 RL = 100 Cload = 5 pF
Min
2.375 100 0.5
Typ
2.5 200 1.2 500
Max
2.625 600 1.5
Unit
V mv V ps
Notes to Table 11-2:
VOD = VOH - VOL. VOS = (VOH + VOL) / 2.
Figure 11-6 shows the RSDS transmitter output signal waveforms. Figure 11-6. Transmitter Output Signal Level Waveforms for RSDS
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VOS Ground
www..com
Differential Waveform (Mathematical Function of Positive & Negative Channel) VOD 0V VOD p - n (1)
Note to Figure 11-6:
(1) The p - n waveform is a function of the positive channel (p) and the negative channel (n).
Altera Corporation November 2004
Preliminary
11-7 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
I/O Standards Support
Designing with RSDS
Cyclone II devices support the RSDS output standard using the LVDS I/O buffer types. For transmitters, the LVDS output buffer can be used with the external resistor network shown in Figure 11-7. Figure 11-7. RSDS Resistor Network
Cyclone II Device 1 inch Resistor Network
Note (1)
LVDS Transmitter
RS 50 RP RS 50 RL = 100
RSDS Receiver
Note to Figure 11-7:
(1) Actual RS and RP values are pending on device characterization.
www..com
A resistor network is required to attenuate the LVDS output voltage swing to meet the RSDS specifications. The resistor network values can be modified to reduce power or improve the noise margin. The resistor values chosen should satisfy the following equation:
R RS x P 2 RS + RP 2
f
For more information on the RSDS I/O standard, see the RSDS specification from the National Semiconductor web site (www.national.com).
= 50
Additional simulations using the IBIS models should be performed to validate that custom resistor values meet the RSDS requirements.
RSDS Software Support
When designing for the RSDS I/O standard, assign the LVDS I/O standard to the I/O pins intended for RSDS in the Quartus(R) II software. Contact Altera Applications for reference designs.
11-8 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
mini-LVDS Standard Support in Cyclone II Devices
The mini-LVDS specification defines its use in chip-to-chip applications between the timing controller and the column drivers on display panels. Cyclone II devices meet the Texas Instruments mini-LVDS Interface Specification and support the mini-LVDS output standard. Table 11-3 shows the mini-LVDS electrical characteristics for Cyclone II devices.
Table 11-3. mini-LVDS Electrical Characteristics for Cyclone II Devices Symbol
VCCIO VOD (1) VOS (2) Tr / Tf
(1) (2)
Parameters
Output supply voltage Differential output voltage Output offset voltage Transition time
Condition
RL = 100 RL = 100 20 to 80%
Min
2.375 300 1
Typ
2.5
Max
2.625 600
Units
V mV mV ps
1.2
1.4 500
Notes to Table 11-3:
VOD = VOH - VOL. VOS = (VOH + VOL) / 2.
www..com
Figure 11-8. Transmitter Output Signal Level Waveforms for mini-LVDS
Single-Ended Waveform VOD VOS Ground
Figure 11-8 shows the mini-LVDS receiver and transmitter signal waveforms.
Positive Channel (p) = VOH Negative Channel (n) = VOL
Differential Waveform VOD 0V VOD
Altera Corporation November 2004
Preliminary
11-9 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
I/O Standards Support
Designing with mini-LVDS
Similar to RSDS, Cyclone II devices support the mini-LVDS output standard using the LVDS I/O buffer types. For transmitters, the LVDS output buffer can be used with the external resistor network shown in Figure 11-9. The resistor values chosen should satisfy the equation on page 11-8. Figure 11-9. mini-LVDS Resistor Network
Cyclone II Device 1 inch Resistor Network
LVDS Transmitter
RS 50 RP RS 50
mini-LVDS Receiver
RL = 100
Note to Figure 11-9:
(1) RS and RP values are pending on silicon characterization.
www..com
mini-LVDS Software Support
When designing for the mini-LVDS I/O standard, assign the LVDS I/O standard to the I/O pins intended for mini-LVDS in the Quartus II software. Contact Altera Applications for reference designs.
11-10 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
LVPECL Support in Cyclone II
The LVPECL I/O standard is a differential interface standard requiring a 3.3-V VCCIO and is used in applications involving video graphics, telecommunications, data communications, and clock distribution. The high-speed, low-voltage swing LVPECL I/O standard uses a positive power supply and is similar to LVDS. However, LVPECL has a larger differential output voltage swing than LVDS. Cyclone II devices support the LVPECL input standard at the clock input pins only. Table 11-4 shows the LVPECL electrical characteristics for Cyclone II devices. Figure 11-10 shows the LVPECL I/O interface.
Table 11-4. LVPECL Electrical Characteristics for Cyclone II Devices Symbol
VCCIO VIH VIL VID
Parameters
Output supply voltage Input high voltage Input low voltage Differential input voltage
Condition
Min
3.135 2,100 0
Typ
3.3
Max
3.465 2,880 2,200
Units
V mV mV mV
Peak to peak
100
600
950
Figure 11-10. LVPECL I/O Interface
LVDS Transmitter
www..com
Cyclone II Receiver Z = 50 100 Z = 50
Altera Corporation November 2004
Preliminary
11-11 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
I/O Standards Support
Differential SSTL Support in Cyclone II Devices
The differential SSTL I/O standard is a memory bus standard used for applications such as high-speed double data rate (DDR) SDRAM interfaces. The differential SSTL I/O standard is similar to voltage referenced SSTL and requires two differential inputs with an external termination voltage (VTT) of 0.5 x VCCIO to which termination resistors are connected. A 2.5-V output source voltage is required for differential SSTL-2, while a 1.8-V output source voltage is required for differential SSTL-18. The differential SSTL output standard is only supported at PLLCLKOUT pins using two single-ended SSTL output buffers programmed to have opposite polarity. The differential SSTL input standard is supported at the global clock (GCLK) pins only, treating differential inputs as two single-ended SSTL, and only decoding one of them.
f
For SSTL signaling characteristics, see the DC Characteristics & Timing Specification chapter and the Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook. Figures 11-11 and 11-12 show the differential SSTL class I and II interfaces, respectively.
Figure 11-11. Differential SSTL Class I Interface
www..com
VTT VTT 50 25 Z0 = 50 25 Z0 = 50 50 Receiver
Output Buffer
11-12 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
Figure 11-12. Differential SSTL Class II Interface
VTT VTT VTT VTT
Output Buffer 25
50
50
50
50
Receiver
Z0 = 50 25 Z0 = 50
Differential HSTL Support in Cyclone II Devices
The differential HSTL AC and DC specifications are the same as the HSTL single-ended specifications. The differential HSTL I/O standard is available on the GCLK pins only, treating differential inputs as two singleended HSTL, and only decoding one of them. The differential HSTL output I/O standard is only supported at the PLLCLKOUT pins using two single-ended HSTL output buffers with the second output programmed as inverted. The standard requires two differential inputs with an external termination voltage (VTT) of 0.5 x VCCIO to which termination resistors are connected. For the HSTL signaling characteristics, see the DC Characteristics & Timing Specifications chapter and the Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook. Figures 11-13 and 11-14 show differential HSTL class I and II interfaces, respectively.
www..com
f
Altera Corporation November 2004
Preliminary
11-13 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
High-Speed I/O Timing in Cyclone II Devices
Figure 11-13. Differential HSTL Class I Interface
VTT VTT
Output Buffer
50
50
Receiver
Z0 = 50
Z0 = 50
Figure 11-14. Differential HSTL Class II Interface
VTT VTT VTT VTT
Output Buffer
50
50
50
50
Receiver
www..com
Z0 = 50 Z0 = 50
High-Speed I/O Timing in Cyclone II Devices
This section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in Cyclone II devices. LVDS, LVPECL, RSDS, and mini-LVDS I/O standards enable high-speed data transmission. Timing for these high-speed signals is based on skew between the data and the clock signals. High-speed differential data transmission requires timing parameters provided by integrated circuit (IC) vendors and requires consideration of board skew, cable skew, and clock jitter. This section provides details on high-speed I/O standards timing parameters in Cyclone II devices.
11-14 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices
Table 11-5 defines the parameters of the timing diagram shown in Figure 11-15. Figure 11-16 shows the Cyclone II high-speed I/O timing budget.
Table 11-5. High-Speed I/O Timing Definitions Parameter
Transmitter channel-tochannel skew Sampling window
Symbol
TCCS
Description
The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid in order for you to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. TSW = TSU + Thd + PLL jitter. RSKM is defined by the total margin left after accounting for the sampling window and TCCS. The RSKM equation is: RSKM = (TUI - SW - TCCS) / 2. Allowed input jitter on the input clock to the PLL that is tolerable while maintaining PLL lock. Peak-to-peak output jitter from the PLL.
SW
Receiver input skew margin
RSKM
Input jitter tolerance (peakto-peak) Output jitter (peak-to-peak)
www..com
Figure 11-15. High-Speed I/O Timing Diagram
External Input Clock Time Unit Interval (TUI) Internal Clock TCCS RSKM Sampling Window (SW) RSKM TCCS Receiver Input Data
Altera Corporation November 2004
Preliminary
11-15 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Design Guidelines
Figure 11-16. Cyclone II High-Speed I/O Timing Budget Note (1)
Internal Clock Period
0.5 x TCCS
RSKM
SW
RSKM
0.5 x TCCS
Note to Figure 11-16:
(1) The equation for the high-speed I/O timing budget is: Period = 0.5/TCCS + RSKM + SW + RSKM + 0.5/TCCS.
Design Guidelines
This section provides guidelines for designing with Cyclone II devices.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the VCCIO supply, there are restrictions on placement of single-ended I/O pins in relation to differential pads. See the guidelines in the Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook for placing singleended pads with respect to differential pads in Cyclone II devices.
www..com
f
Board Design Considerations
This section explains how to get the optimal performance from the Cyclone II I/O interface and ensure first-time success in implementing a functional design with optimal signal quality. The critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques must be considered to get the best performance from the IC. The Cyclone II device generates signals that travel over the media at frequencies as high as 805 Mbps. Use the following general guidelines for improved signal quality:
Base board designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces.
11-16 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U
www..com
High-Speed Differential Interfaces in Cyclone II Devices

www..com
Conclusion
Maintain equal distance between traces in LVDS pairs, as much as possible. Routing the pair of traces close to each other will maximize the common-mode rejection ratio (CMRR). Longer traces have more inductance and capacitance. These traces should be as short as possible to limit signal integrity issues. Place termination resistors as close to receiver input pins as possible. Use surface mount components. Avoid 90 or 45 corners. Use high-performance connectors. Design backplane and card traces so that trace impedance matches the connector's and/or the termination's impedance. Keep equal number of vias for both signal traces. Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the channel-to-channel skew (TCCS) value increases. Limit vias because they cause discontinuities. Use the common bypass capacitor values such as 0.001, 0.01, and 0.1 F to decouple the high-speed PLL power and ground planes. Keep switching transistor-to-transistor logic (TTL) signals away from differential signals to avoid possible noise coupling. Do not route TTL clock signals to areas under or above the differential signals. Analyze system-level signals.
For PCB layout guidelines, see AN 224: High-Speed Board Layout Guidelines. Cyclone II differential I/O capabilities enable you to keep pace with increasing design complexity. Support for I/O standards including LVDS, LVPECL, RSDS, mini-LVDS, differential SSTL and differential HSTL allows Cyclone II devices to fit into a wide variety of applications. Taking advantage of these I/O capabilities and Cyclone II pricing allows you to lower your design costs while remaining on the cutting edge of technology.
Altera Corporation November 2004
Preliminary
11-17 Cyclone II Device Handbook, Volume 1
www..com www..com 4U
www..com
Conclusion
www..com
11-18 Cyclone II Device Handbook, Volume 1
Preliminary
Altera Corporation November 2004
www..com www..com 4U

▲Up To Search▲

Price & Availability of EP2C8

	To Download EP2C8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .